SLG74190 Description
Use 475Ω , 1% for 100Ω trace. Use 412Ω, 1% for 85Ω trace. 3.3V tolerant input for input/output frequency selection.
SLG74190 Key Features
- Intel DB1900Z Clock Specification Revision 1.0
- 1:19 Differential Zero Delay Buffer
- PCIe Gen 2/Gen3 & Intel ® QPI
- 100ps Input to Output Delay
- HCSL Output Buffer
- Configuration PLL (ZDB) and Bypass Mode
- Programmable PLL Bandwidth
- 72 pin QFN package (6/6 RoHS pliant)
- differential clock output pairs @ 0.7V
- OE# input pins to control output