SLG74190
Overview
- Intel DB1900Z Clock Specification Revision 1.0
- 1:19 Differential Zero Delay Buffer
- PCIe Gen 2/Gen3 & Intel ® QPI
- 100ps Input to Output Delay
- HCSL Output Buffer
- Configuration PLL (ZDB) and Bypass Mode
- Programmable PLL Bandwidth
- 72 pin QFN package (6/6 RoHS Compliant) SLG74190 1 to 19 Differential Clock Buffer Output Summary
- 19 - differential clock output pairs @ 0.7V
- 8 - OE# input pins to control output
