Datasheet Summary
Cost-Effective, 2A Sink/Source Bus Termination Regulator
General D escription
The RT9173C is a si mple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to ply with the JEDEC SSTL_2 a nd SSTL_18 or other spe cific interfaces such a s HSTL, SCSI-2 a nd SCSI-3 etc. device s requirements. The regulator is ca pable of a ctively sinking or sourcing up to 2Awhile regulating a n output voltage to within 40mV . The output termin ation voltage ca b be tightly regulated to tra ck 1/2VDDQ by two extern al voltage divider resistors or the de sired output voltage ca n be pro-gra mmed by externally forcing the...
