FEATURES
z System Operation Dual Core Architecture (ARM9 + DSP) , including hardware accelerator Support system boot sequentially from ARM to DSP Support address remap function For two cores, all modules have unified address space Selectable JTAG debug method ARM9 debug only (default) DSP debug only ARM9+DSP dual core debug Selectable CPU booting method Boot from NOR Flash Boot from Nand Flash Boot from SPI nor flash Boot from UART device Boot from Host interface z Memory Organization Internal memory space for ARM processor Internal 16KB SRAM for ARM9 ICache Internal 16KB SRAM for ARM9 DCache Internal 8KB SRAM for ARM9 ITCM Internal 16KB SRAM for ARM9 DTCM Internal memory space for DSP processor Internal 96KB SRAM for DSP Instruction L1 Memory (Also config as 32KB Memory+32KB ICache by software, another 32KB is switched by software) Internal 64KB SRAM for DSP Data L1 Memory Internal 48KB SRAM for DSP Instruction L2 Memory Internal 32KB SR...
Rockchip
