H5TQ1G83EFR-xxC Overview
The H5TQ1G6(8)3EFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of...
H5TQ1G83EFR-xxC Key Features
- DQ Power & Power supply : VDD & VDDQ = 1.5V +/0.075V
- DQ Ground supply : VSSQ = Ground
- Fully differential clock inputs (CK, CK) operation
- Differential Data Strobe (DQS, DQS)
- On chip DLL align DQ, DQS and DQS transition with CK transition
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable additive latency 0, CL-1, and CL-2 supported
- Programmable burst length 4/8 with both nibble sequential and interleave mode
- Programmable PASR(Partial Array Self-Refresh) for Digital consumer
