H5TQ1G83EFR-xxC Datasheet | SK Hynix

1Gb DDR3 SDRAM 1Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS pliant) H5TQ1G83EFR-xxC H5TQ1G83EFR-xxI H5TQ1G83EFR-xxL http://../ H5TQ1G83EFR-xxJ H5TQ1G63EFR-xxC H5TQ1G63EFR-xxI H5TQ1G63EFR-xxL H5TQ1G63EFR-xxJ - SK hynix Inc. reserves the right to change products or specifications without notice Rev. 1.0 /May. 2012 1 Revision History Revision No. 1.0 History Preliminary version release Date May. 2012 Remark http://../ Rev. 1.0 /May. 2012 2 Description The H5TQ1G6(8)3EFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix Inc. 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information Features - DQ Power & Power supply : VDD & VDDQ = 1.5V +/0.075V - DQ Ground supply : VSSQ = Ground - Fully differential clock inputs (CK, CK) operation - Differential Data Strobe (DQS, DQS) - On chip DLL align DQ, DQS and DQS transition with CK transition - DM masks write data-in at the both rising and falling edges of the data strobe - All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock - Programmable CAS latency 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported - Programmable additive latency 0, CL-1, and CL-2 supported - Programmable CAS Write latency (CWL) =...