S29WS512N Datasheet | SPANSION

features between the two flash device cores. Table 1.1 parison of Key Features Futures Technology Process Rule VCC VIO (VCCQ) Max Density Configuration Register Sector Architecture Bank Architecture Bank Size Boot Option mon Flash Interface (CFI) Simultaneous Read/Write Asynchronous Read Mode Page Mode Read Page Size Synchronous (Burst) Read Mode Burst Frequency Burst Length Single Word / Write Buffer Program Write Buffer Size Program Suspend / Program Resume Sector Erase / Chip Erase Erase Suspend / Erase Resume Unlock Bypass / Fast Mode Accelerated Program / Chip Erase Sector Protection Secured Silicon Area S29WS256N Mirror Bit ™ S29WS512P Mirror Bit™ 90 nm 1.70 V to 1.95 V =VCC 512 Mb CR0.0 - CR0.15, CR1.0 - CR1.15 16 K-words Small Sector 64 K-words Large Sector 16 Bank Structure 4 Mb Top / Bottom / Dual Yes Yes Yes Yes 8-words Yes 54 MHz / 66 MHz / 80 MHz / 108 MHz 8 / 16 / 32 Continuous Yes 32-words Yes Yes Yes Yes Yes Hardware: WP# Software: ASP 128-words factory locked 128-words customer lockable 110 nm 1.70 V to 1.95 V =VCC 256 Mb CR0-CR15 16 K-words Small Sector 64 K-words Large Sector 16 Bank Structure 2 Mb Top / Bottom / Dual Yes Yes Yes Yes 4-words Yes 54 MHz / 66 MHz / 80 MHz 8 / 16 / 32 Continuous Yes 32-words Yes Yes Yes Yes Yes Hardware: WP# Software: ASP 128-words factory locked 128-words customer lockable Publication Number 2x WS-N_to_WS-P_AN Revision 01E Issue Date October 3, 2006 A pplication Note 2. Performance Characteristics The 90 nm Mirror Bit™ technology, on which the S29WS512P is based, allows performance improvements over the S29WS256N, which is based on 110 nm Mirror Bit technology. Table 2.1 shows the performance parison between the two devices. Table 2.1 Performance parison Access Time Read Access Time VCC=1.70 V to 1.95 V CL=30p F Max. Async. Access (t ACC) Max. Async. Page Access (t PACC) Max. Sync. Burst Access (t BACC) Typ Single Word Programming Time Max (See Note) Typ Total 32-Words Buffer Programming Time Max (See Note) Typ...