Datasheet4U Logo Datasheet4U.com

M54HCT75 - 4 BIT D TYPE LATCH

Datasheet Summary

Description

TheM54/74HCT75 isahigh speedCMOS4-BITD-TYPE LATCH fabricated in silicon gate C2MOS technology.

It has the same high speed performance of LSTTL combined withtrueCMOSlow power consumption.

2 or G3

4).

📥 Download Datasheet

Datasheet preview – M54HCT75

Datasheet Details

Part number M54HCT75
Manufacturer STMicroelectronics
File Size 239.65 KB
Description 4 BIT D TYPE LATCH
Datasheet download datasheet M54HCT75 Datasheet
Additional preview pages of the M54HCT75 datasheet.

📁 Similar Datasheet

  • M54HCT74 - Rad-hard high speed 2V to 6V CMOS logic (STMicroelectronics)
  • M54HCT158 - QUAD 2 CHANNEL MULTIPLEXER (STMicroelectronics)
  • M54HCT244 - Rad-hard high speed 2V to 6V CMOS logic (STMicroelectronics)
  • M54HCT245 - Rad-hard high speed 2V to 6V CMOS logic (STMicroelectronics)
  • M54HC00 - Rad-hard high speed 2V to 6V CMOS logic (STMicroelectronics)
  • M54HC02 - Rad-hard high speed 2V to 6V CMOS logic (STMicroelectronics)
  • M54HC03 - Rad-hard high speed 2V to 6V CMOS logic (STMicroelectronics)
  • M54HC04 - Rad-hard high speed 2V to 6V CMOS logic (STMicroelectronics)
  • M54HC08 - Rad-hard high speed 2V to 6V CMOS logic (STMicroelectronics)
  • M54HC10 - Rad-hard high speed 2V to 6V CMOS logic (STMicroelectronics)
Other Datasheets by ST Microelectronics

Full PDF Text Transcription

Click to expand full text
M54HCT75 M74HCT75 4 BIT D TYPE LATCH . . . . . . HIGH SPEED tPD = 15 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2 V (MIN.) VIL = 0.8 V (MAX.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) PIN AND FUNCTION COMPATIBLE WITH 54/74LS75 B1R (Plastic Package) F1R (Ceramic Package) DESCRIPTION TheM54/74HCT75 isahigh speedCMOS4-BITD-TYPE LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined withtrueCMOSlow power consumption. Itcontains two groups of 2-bit latches controlled by an enable input (G1 • 2 or G3 • 4). These two latch groups can be used indifferent circuits. Each latch has Q and Q outputs (1Q 4Q and 1Q - 4Q).
Published: |