ST10F166 Datasheet | STMicroelectronics

Feature Protection-Optional Flash Memory Dedicated Flash Control Register with Operation Lock Mechanism 12 V External Flash Programming Voltage Flash Program Verify and Erase Verify Modes 1000 Flash Program/Erase Cycles guaranteed Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/ Data Buses Hold and Hold-Acknowledge Bus Arbitration Support 512 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) PQFP100 s s s s s s s s s s 16-Priority-Level Interrupt System 10-Channel 10-bit A/D Converter with 9.7 µs Conversion Time (ST10F166) 16-Channel Capture/pare Unit Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (USARTs) Programmable Watchdog Timer Up to 76 General Purpose I/O Lines Supported by a Wealth of Development Tools like C-pilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 100-Pin Plastic PQFP Package February 1996 This is preliminary information from SGS-THOMSON. Details are subject to change without notice. 1/62 Table of Contents Page Number - - - - - - - - . . . . 1 1 INTRODUCTION - - - - - - - - - . . 3 2 MEMORY ORGANIZATION - - - - - - - . . . 8 3 EXTERNAL BUS CONTROLLER - - - - - - . . . . 9 4 FLASH MEMORY - - - - - - - - - 11 5 FLASH MEMORY PROGRAMMING AND ERASURE - - - . . 12 6 FLASH MEMORY SECURITY - - - - . . ....