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ST10F268 - 16-BIT MCU

General Description

MEMORY ORGANIZATION FLASH MEMORY PROGRAMMING / ERASING WITH ST EMBEDDED ALGORITHM KERNEL PROGRAMMING EXAMPLES FLASH MEMORY CONFIGURATION FLASH PROTECTION BOOTSTRAP LOADER MODE CENTRAL PROCESSING UNIT (CPU) INSTRUCTION SET SUMMARY EXTERNAL BUS CONTROLLER INTERRUPT SYSTEM CAPTURE / COMPARE (CAP

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ST10F168 16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM s HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE – 80ns INSTRUCTION CYCLE TIME AT 25MHz CPU CLOCK – 400ns 16 X 16-BIT MULTIPLICATION – 800ns 32 / 16-BIT DIVISION – ENHANCED BOOLEAN BIT MANIPULATION FACILITIES – ADDITIONAL INSTRUCTIONS TO SUPPORT HLL AND OPERATING SYSTEMS – SINGLE-CYCLE CONTEXT SWITCHING SUPPORT PQFP144 (28 x 28 mm) (Plastic Quad Flat Pack) s s s s s s s MEMORY ORGANIZATION – 256K BYTE ON-CHIP FLASH MEMORY – 10K ERASING / PROGRAMMING CYCLES – UP TO 16M BYTE LINEAR ADDRESS SPACE FOR CODE AND DATA (5M BYTE WITH CAN) – 2K BYTE ON-CHIP INTERNAL RAM (IRAM) – 6K BYTE ON-CHIP EXTENSION RAM (XRAM) – 20 YEAR DATA RETENTION TIME FAST AND FLEXIBLE BUS – PROGRAMMABLE EXTERNAL BUS CHARACTE- RISTICS FOR DIFFEREN