ST10F280 Description
14 3 Functional description . 26 4 Memory organization . 27 4.1 Visibility of XBUS peripherals.
ST10F280 Key Features
- High performance cpu with dsp functions
- 16-bit CPU with 4-stage pipeline
- 50ns Instruction cycle time at 40MHz CPU clock
- Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator
- Repeat unit
- Enhanced boolean bit manipulation facilities
- Additional instructions to support hll and operating systems
- Single-cycle context switching support
- Memory organization
- 512KB on-chip Flash memory single voltage with erase/program controller