ST1305 Datasheet | STMicroelectronics

DESCRIPTION The ST1305 is a 192-bit EEPROM device with associated security logic to control memory access. The circuit includes counting capabilities and thus is very well adapted to prepaid card applications. The ST1305 is protected by hard-wired security logic GND and special fuses. The memory is arranged as a matrix of 24x8 cells, accessed in a serial bit-wise fashion for reading and programming, and in a byte-wise fashion Table 1. Signal Names for internal erasing. CLK Clock The device recognises three mands issued via the RST and CLK pins (as described in the full data sheet): - RESET: to reset the internal address register to 00d - READ: to increment the internal address register, and read the data bit at that address - PROG: to program the bit at the current address. RST I/O VCC GND Reset Serial Data Input/Output Supply Voltage Ground AI01032 BD.05/9803V1 1/2 The device offers two distinct configurations: - ISSUER: for the card manufacturer, allowing special data to be written to the chip, during initialisation - USER: for the end user of the card, restricting access to the chip. Before delivery, from ST to the card issuer, the device is placed in the ISSUER configuration. This operation is performed by blowing the “test fuse”. Figure 3. Memory Map In USER Configuration 000d 016d Card Identification 48 bits EEPROM Cells Matrix Circuit Identification 16 bits READ ONLY 064d Counters / Transport Code 48 bits READ, WRITE, ERASE Certificate / Transport Code 128d Issuer Defined Area 192d Unused 260d 64 bits READ ONLY 16 bits 112d Fuses DS0502 ORDERING INFORMATION SCHEME For a full list of the available options, please see the current Memory Shortform Catalogue. For further information on any aspect of this device, please contact your nearest ST Sales Office. Example: - W2 / XX YY DS0501 Delivery Form U: Micromodule on reel W2: Wafer 280 µm thickness Customer Code Transport Code Given by...