ST1355 Datasheet | STMicroelectronics

DESCRIPTION The members of the ST1335/1336/1355 family are principally designed for use in prepaid Phonecard applications. Each is a 272-bit EEPROM device, with associated security logic and special fuses to control memory access. The memory is arranged as a matrix of 34 x 8 cells, accessed in a serial bitwise fashion for reading and programming, and in a byte-wise fashion for internal erasing. An on-chip Figure 1. Logic Diagram Table 1. Signal Names CLK RST I/O VCC GND Clock Reset Data Input / Output Supply Voltage ST1335 ST1336 ST1355 CLK I/O Ground AI03106b October 1999 plete data available under NDA. 1/3 ST1335, ST1336, ST1355 Figure 2. Memory Map 0 16 Physical EEPROM Cells 32 bits 0 16 masked bits Circuit Identification Area Card Identification Area (ID) RAM1 (Write-Only) (RN) (ST1335, ST1355) 48 bits Data Area (CD) 40 bits 8 bits 16 bits (Counters and Transport Code) Reserved Area (RA) Certificate (CER) Issuer-Defined Area (ST1336) 64 bits Authentication Secret Key (SK) (ST1335, ST1355) 104 112 128 Physical EEPROM Cells Reserved Area (RA) 256 260 264 288 Physical EEPROM Cells 32 bits Anti-Tearing Flags 320 4 bits 4 bits 24 bits Signature Fuses Unused 56 bits User-Defined Area AI03385 Note: 1. The write-only RAM area (RN) is applicable only for the User Configuration. address counter provides an internal address space of up to 512 bits. Each member of the ST1335/1336/1355 family has an identification data area, unit-counters (with an anti-tearing mechanism for reliable usage in open readers), a post validation certificate, an issuer area (ST1336) or an authentication secret key area (ST1335/1355), and a user area. This is summarized in Figure 2. The validation certificate allows the recognition of the device by the appropriate security module. The anti-tearing mechanism guards against extra, spurious count signals being executed when the 2/3 ST1335, ST1336, ST1355 card is unexpectedly extracted, while an...