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ST20-GP1 - GPS PROCESSOR

General Description

51 Strobe allocation 52 External accesses 52 2/116 ® ST20-GP1 9.4 9.5 9.6 MemWait 56 EMI configuration registers 58 Reset and bootstrap behavior 59 10 Clocks and low power controller

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Key Features

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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® ST20-GP1 GPS PROCESSOR ENGINEERING DATA FEATURES s Application specific features • 12 channel GPS correlation DSP hardware and ST20 CPU (for control and position caluculations) on one chip • no TCXO required • RTCA-SC159 / WAAS / EGNOS supported s GPS performance • accuracy - stand alone with SA on <100m, SA off <30m - differential <1m - surveying <1cm • time to first fix - autonomous start 90s - cold start 45s - warm start 7s - obscuration 1s s 32-bit ST20 CPU • 16/33 MHz processor clock • 25 MIPS at 33 MHz • fast integer/bit operations s 4 Kbytes on-chip SRAM • 130 Mbytes/s maximum bandwidth s Programmable memory interface • 4 separately configurable regions • 8/16-bits wide • support for mixed memory • 2 cycle external access s Serial communications • Programmable UART (ASC) • OS-Li