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ST20-GP6 - GPS PROCESSOR

General Description

58 External accesses 59 MemWait 60 EMI configuration registers 62 Boot source 65 Default configuration 65 11 Low power controller

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Key Features

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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® ST20-GP6 GPS PROCESSOR PRELIMINARY DATA FEATURES s Application specific features • 12 channel GPS correlation DSP hardware, ST20 CPU (for control and position calculations) and memory on one chip • no TCXO required • RTCA-SC159 / WAAS / EGNOS supported s GPS performance • accuracy - stand alone with SA on <100m, SA off <30m - differential <1m - surveying <1cm • time to first fix - autonomous start 90s - cold start 45s - warm start 7s - obscuration 1s s Enhanced 32-bit VL-RISC CPU - C2 core • 16/33/50 MHz processor clock • 25 MIPS at 33 MHz • fast integer/bit operations s 64 Kbytes on-chip SRAM s 128 Kbytes on-chip ROM s Programmable memory interface • 4 separately configurable regions • 8/16-bits wide • support for mixed memory • 2 cycle external access s Programmable UART (ASC) s Para