DESCRIPTION
These flip-flop are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and CLEAR input and Q and Q outputs. CLEAR is independent of the clock and accomplished by a logic low on the input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection October 1992 1/11 M54/M74HC107 TRUTH TABLE INPUTS CLR L H H H H H X: Don’t Care OUTPUTS K X L H L H X CK X Q L Qn L H Qn Qn Q H Qn H L Qn Qn J X L L H H X FUNCTION CLEAR NO CHANGE TOGGLE NO CHANGE PIN DESCRIPTION
PIN No 1, 8, 4, 11 2, 6 3, 5 12, 9 13, 10 7 14 SYMBOL 1J, 2J, 1K, 2K 1Q, 2Q 1Q, 2Q 1CK, 2CK 1CLR, 2CLR GND V CC NAME AND FUNCTION Synchronous Inputs; Flip-Flop 1 And 2 Complement Flip-Flop Outputs True Flip-Flop Outputs Clock Input Asynchronous Reset Inputs Ground (0V) Positive Supply Voltage IEC LOG...
STMicroelectronics
