STMicroelectronics 74AUP1G04
The 74AUP1G04 is a low voltage CMOS single inverter gate fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.2 to 3.6 V operations and low power and low noise applications.FEATURES
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● High speed: tPD = 4.3 ns (max.) at VCC = 2.3 V Power down protection on inputs and outputs Balanced propagation delays: tPLH ≈ tPHL Operating voltage range: VCC (opr) = 1.2 to 3.6 V Low power dissipation: ICC = 1 µA (max.) at TA = 85 °C Latch-up performance exceeds 300 mA (JESD 78, Class II) ESD performance: – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SOT-665 DFN6L
APPLICATIONS
●● Mobile phones Personal digital assistants (PDAs)
DESCRIPTION
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2kV ESD immunity and transient excess voltage. Table 1. Device summary Order code 74AUPG04DTR 74AUPG04GTR Package DFN6L (1.2 x 1 mm) SOT-665 (1.6 x 1.6 mm) Packing Tape and reel Tape and reel March 2008 Rev 1 1/18 18 Pin settings 74AUP1G04 1 1.1 Pin settings Pin connection Figure 1. Pin connection (top through view) NC A GND 1 2 3 6 5 4 VCC NC B NC A GND 1 2 3 5 VCC 4 B DFN6L SOT-665 CS00092 1.2 Pin description Table 2.