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74AUP1G04 - Low power single inverter gate

Datasheet Summary

Description

The 74AUP1G04 is a low voltage CMOS single inverter gate fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

It is ideal for 1.2 to 3.6 V operations and low power and low noise applications.

Features

  • High speed: tPD = 4.3 ns (max. ) at VCC = 2.3 V Power down protection on inputs and outputs Balanced propagation delays: tPLH ≈ tPHL Operating voltage range: VCC (opr) = 1.2 to 3.6 V Low power dissipation: ICC = 1 µA (max. ) at TA = 85 °C Latch-up performance exceeds 300 mA (JESD 78, Class II) ESD performance:.
  • 2000-V Human-Body Model (A114-A).
  • 200-V Machine Model (A115-A).
  • 1000-V Charged-Device Model (C101) SOT-665 DFN6L Appli.

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Datasheet Details

Part number 74AUP1G04
Manufacturer STMicroelectronics
File Size 438.20 KB
Description Low power single inverter gate
Datasheet download datasheet 74AUP1G04 Datasheet
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www.DataSheet4U.com 74AUP1G04 Low power single inverter gate Features ■ ■ ■ ■ ■ ■ ■ High speed: tPD = 4.3 ns (max.) at VCC = 2.3 V Power down protection on inputs and outputs Balanced propagation delays: tPLH ≈ tPHL Operating voltage range: VCC (opr) = 1.2 to 3.6 V Low power dissipation: ICC = 1 µA (max.) at TA = 85 °C Latch-up performance exceeds 300 mA (JESD 78, Class II) ESD performance: – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SOT-665 DFN6L Applications ■ ■ Mobile phones Personal digital assistants (PDAs) Description The 74AUP1G04 is a low voltage CMOS single inverter gate fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.2 to 3.
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