| Part Number | 74AUP1G04 Datasheet |
|---|---|
| Manufacturer | Nexperia |
| Overview |
The 74AUP1G04 is a single inverter.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ens.
and benefits
* Wide supply voltage range from 0.8 V to 3.6 V * CMOS low power dissipation * High noise immunity * Complies with JEDEC standards: * JESD8-12 (0.8 V to 1.3 V) * JESD8-11 (0.9 V to 1.65 V) * JESD8-7 (1.65 V to 1.95 V) * JESD8-5 (2.3 V to 2.7 V) * JESD8C (2.7 V to 3.6 V) * ESD protection. |
74AUP1G04 Datasheet and Specifications PDF
The 74AUP1G04 is a Low-power inverter.
| Part Number | 74AUP1G04 Datasheet |
|---|---|
| Description | Low-power inverter |
| Manufacturer | NXP Semiconductors |
| Overview | The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit toleran. s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-C Class 3A. Exceeds 50. |
| Part Number | 74AUP1G04 Datasheet |
|---|---|
| Description | Low power single inverter gate |
| Manufacturer | STMicroelectronics |
| Overview |
The 74AUP1G04 is a low voltage CMOS single inverter gate fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.2 to 3.6 V operations and low power a.
* * * * * * * High speed: tPD = 4.3 ns (max.) at VCC = 2.3 V Power down protection on inputs and outputs Balanced propagation delays: tPLH ≈ tPHL Operating voltage range: VCC (opr) = 1.2 to 3.6 V Low power dissipation: ICC = 1 µA (max.) at TA = 85 °C Latch-up performance exceeds 300 mA (JESD 78, Cl. |
| Part Number | 74AUP1G04 Datasheet |
|---|---|
| Description | SINGLE INVERTER GATE |
| Manufacturer | Diodes Incorporated |
| Overview |
The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.
The 74AUP1G04 is a single inverter gate with a standard push-pull ou.
* Advanced Ultra Low Power (AUP) CMOS * Supply Voltage Range from 0.8V to 3.6V * ±4 mA Output Drive at 3.0V * Low Static Power Consumption ICC < 0.9µA * Low Dynamic Power Consumption CPD = 6.1pF (Typical at 3.6V) * Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise. |