Datasheet4U Logo Datasheet4U.com

74LVQ574 - OCTAL D-TYPE FLIP FLOP

Datasheet Summary

Description

The LVQ574 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron 2 silicon gate and double-layer metal wiring C MOS technology.

It is ideal for low power and low noise 3.3V applications.

📥 Download Datasheet

Datasheet preview – 74LVQ574

Datasheet Details

Part number 74LVQ574
Manufacturer STMicroelectronics
File Size 75.15 KB
Description OCTAL D-TYPE FLIP FLOP
Datasheet download datasheet 74LVQ574 Datasheet
Additional preview pages of the 74LVQ574 datasheet.

📁 Similar Datasheet

  • 74LVQ573 - Low Voltage Octal Latch (Fairchild Semiconductor)
  • 74LVQ00 - Low Voltage Quad 2-Input NAND Gate (Fairchild Semiconductor)
  • 74LVQ02 - Low Voltage Quad 2-Input NOR Gate (Fairchild Semiconductor)
  • 74LVQ04 - Low Voltage Hex Inverter (Fairchild Semiconductor)
  • 74LVQ08 - Low Voltage Quad 2-Input AND Gate (Fairchild Semiconductor)
  • 74LVQ125 - Low Voltage Quad Buffer (Fairchild Semiconductor)
  • 74LVQ138 - Low Voltage 1-of-8 Decoder/Demultiplexer (Fairchild Semiconductor)
  • 74LVQ14 - Low Voltage Hex Inverter (Fairchild Semiconductor)
  • 74LVQ151 - Low Voltage 8-Input Multiplexer (Fairchild Semiconductor)
  • 74LVQ157 - Low Voltage Quad 2-Input Multiplexer (Fairchild Semiconductor)
Other Datasheets by STMicroelectronics

Full PDF Text Transcription

Click to expand full text
® 74LVQ574 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING s s s s s s s s s s s HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.5 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVQ574M 74LVQ574T On the positive transition of the clock, the Q outputs will be set to logic state that were setup at the D inputs.
Published: |