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74V1G77 - SINGLE D-TYPE LATCH

Description

O wiring C2MOS technology.

It is designed to - operate from 2V to 5.5V, making this device ideal t(s) for portable applications.

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Datasheet preview – 74V1G77

Datasheet Details

Part number 74V1G77
Manufacturer STMicroelectronics
File Size 127.67 KB
Description SINGLE D-TYPE LATCH
Datasheet download datasheet 74V1G77 Datasheet
Additional preview pages of the 74V1G77 datasheet.

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Full PDF Text Transcription

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74V1G77 SINGLE D-TYPE LATCH s HIGH SPEED: tPD = 4.4ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) ) s POWER DOWN PROTECTION ON INPUTS t(s s SYMMETRICAL OUTPUT IMPEDANCE: c |IOH| = IOL = 8mA (MIN) at VCC = 4.5V u s BALANCED PROPAGATION DELAYS: d tPLH ≅ tPHL ro s OPERATING VOLTAGE RANGE: P VCC(OPR) = 2V to 5.5V s IMPROVED LATCH-UP IMMUNITY lete DESCRIPTION o The 74V1G77 is an advanced high-speed CMOS bs SINGLE D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal O wiring C2MOS technology. It is designed to - operate from 2V to 5.5V, making this device ideal t(s) for portable applications. The single D-Type latch is controlled by a Latch c Enable Input (LE).
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