DESCRIPTION
o u While the LE input is held at a high level, the Q d output will follow the data input precisely. When SOT23-5L SOT323-5L ORDER CODES PACKAGE SOT23-5L SOT323-5L T&R 74V1G77STR 74V1G77CTR the LE input is taken low the Q output is latched precisely at the logic level of D input data. Power down protection is provided on inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It’s available in the commercial and extended temperature range. All inputs and output are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. Obsolete Pro PIN CONNECTION AND IEC LOGIC SYMBOLS April 2004 1/10 74V1G77 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN N° 1 2 4 3 5 SYMBOL D LE Q GND VCC NAME QND FUNCTION Data Input Latch Enable Input Data Output Ground (0V) Positive Supply Voltage TRUTH TABLE D LE Q L L No Change * t(s) H L No Change * L H Qn c H H Qn du (*) Q output is latched at the time when the le input is taken low logic level.
STMicroelectronics
