DESCRIPTION
Information signals applied to D inputs are transfered to the Q outputs on the positive going edge of the clock pulse. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS March 2000 1/10 74VHCT174A INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2,5, 7,10, 12, 15 3,4, 6,11, 13, 14 9 SYMBOL CLEAR Q0 to Q5 D0 to D5 CLOCK NAME AND FUNCT ION Asyncronous Master Reset (Active LOW) Flip-Flop Outputs Data Inputs Clock Input (LOW-to-HIGH, EdgeTriggered) Ground (0V) Positive Supply Voltage 8 16 GND VCC TRUTH TABLE INPUTS CL EAR L H H H X:Don’t Care OUT PUT S CLO CK X Q L L H Qn F UNCTIO N CLEAR D X L H X NO CHANGE LOGIC DIAGRAM Thislogic diagram has notbe used to estimate p...
STMicroelectronics
