FEATURES
SUMMARY s SUPPLY VOLTAGE – VDDF = VDDS =1.9V to 2.1V s s s Figure 1. Packages – VPPF = 12V for Fast Program (optional) ACCESS TIME: 85,100ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M36DR432C: 00A4h – Bottom Device Code, M36DR432D: 00A5h FBGA FLASH MEMORY s 32 Mbit (2Mb x16) BOOT BLOCK – Parameter Blocks (Top or Bottom Location) s Stacked LFBGA66 (ZA) 8 x 8 ball array PROGRAMMING TIME – 10µs typical – Double Word Programming Option s ASYNCRONOUS PAGE MODE READ – Page width: 4 Word – Page Mode Access Time: 35ns s DUAL BANK OPERATION – Read within one Bank while Program or Erase within the other – No Delay between Read and Write Operations s BLOCK PROTECTION ON ALL BLOCKS – WPF for Block Locking COMMON FLASH INTERFACE – 64 bit Security Code s s s s SRAM 4 Mbit (256K x 16 bit) LOW VDDS DATA RETENTION: 1V POWER DOWN FEATURES
USING TWO CHIP ENABLE INPUTS November 2001 This is preliminary information on a new product now in development or undergoing evaluation.
STMicroelectronics
