FEATURES
USING TWO CHIP ENABLE INPUTS LOW VCC DATA RETENTION: 2V 1/35 s May 1999 This is information on a product still in production but not recommended for new designs. M36W108T, M36W108B Figure 2. LBGA and LGA Connections (Top View) 1 2 3 4 5 6 A W A14 A11 G A10 E1S B VCCS A18 A8 DQ7 DQ5 VSS C A17 NC A5 DQ4 DQ2 DQ1 D VSS EF NC DQ0 A0 A1 E NC NC DQ3 A6 A3 A2 F NC VCCF NC A19 A7 A4 G NC DQ6 A13 RP RB E2S H NC A12 NC A16 A15 A9 AI02508 Table 1. Signal Names A0-A16 A17-A19 DQ0-DQ7 EF E1S, E2S G W RP RB VCCF VCCS VSS Address Inputs Address Inputs for Flash Chip Data Input/Outputs, Command Inputs for Flash Chip Chip Enable for Flash Chip Chip Enable for SRAM Chip Output Enable Write Enable Reset for Flash Chip Ready/Busy Output for Flash Chip Supply Voltage for Flash Chip Supply Voltage for SRAM Chip Ground DESCRIPTION
The M36W108 is multi-chip device containing an 8 Mbit boot block Flash memory and a 1 Mbit of SRAM. The device is offered in the new Chip Scale Package solutions: LBGA48 1.0 mm ball pitch and LGA48 1.0 mm land pitch.
STMicroelectronics
