DESCRIPTION
The 54HC365 is an advanced high-speed CMOS HEX BUS BUFFER (3-STATE) fabricated with silicon gate C2MOS technology. All six buffers are controlled by the combination of two enable inputs (G1 and G2); all outputs of these buffers are enabled only when both G1 and G2 inputs are held low, under all other conditions these outputs are disabled in a high-impedance state. The M54HC365 has non inverting outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION May 2004 Rev. 1 1/11 M54HC365 Figure 1: IEC Logic Symbols Figure 2: Input And Output Equivalent Circuit Table 1: Pin DESCRIPTION
PIN N° 1, 15 2, 4, 6, 10, 12, 14 3, 5, 7, 9, 11, 13 8 16 SYMBOL G1, G2 1A to 6A 1Y to 6Y GND VCC NAME AND FUNCTION Output Enable Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage Table 2: Truth Table INPUTS G1 L L H X X : Don’t Care Z : High Impedance OUTPUTS An L H X X Y L H Z Z G2 L L X H 2/11 M54HC365 Table 3:...
STMicroelectronics
