DESCRIPTION
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. February 1993 NC = No Internal Connection 1/11 M54/M74HC377 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS G H L L X X: DON’T CARE OUTPUT DATA X L H X Q NO CHANGE L H NO CHANGE CLOCK X LOGIC DIAGRAM 2/11 M54/M74HC377 PIN DESCRIPTION
PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL ENABLE G 1Q to 8Q NAME AND FUNCTION Data Enable Input (Active LOW) Flip Flop Outputs IEC LOGIC SYMBOL 1D to 8D Data Inputs CLOCK GND V CC Clock Input (LO...
STMicroelectronics
