DESCRIPTION
These8-bit D-type flip-flops are controlled by a clock input (CK) and an ouput enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs (HC574) or their complements (HC564). While the OE input is low, the eight outputs will be in a normal logic state (high or low logic level), and while high level, the outputs will be in a high impedPIN CONNECTION (top view) ance state. The output control does not affect the internal operation of flip-flops. That is, the old data can be retained or the new data can be entered even while the outputs are off. The application engineer has a choice of combination of inverting and non-inverting outputs. The 3-state output configuration and the wide choice of outline make bus-organized systems simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. March 1993 1/13 M54/M74HC564/574 INPUT AND OUTPUT EQUIVALENT CIRC...
STMicroelectronics
