DESCRIPTION
While the LE input is held at a high level, the Q outputs will follow the data input precisely. DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC573B1R M74HC573M1R T&R M74HC573RM13TR M74HC573TTR While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while is at high level the outputs will be in a high impedance state. The 3-State output configuration and the wide choice of outline make bus organized system simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 M74HC573 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 NAME AND FUNCTION 3 State Output Enable Input (Active LOW) Data Inputs Q0 to Q7 3 State Latch Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OE LE HX LL LH LH X: Don’t Care Z: High Impedance (*): Q Outputs are latched at the time when the LE input is taken low logic level.
STMicroelectronics
