DESCRIPTION
On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC574B1R M74HC574M1R T&R M74HC574RM13TR M74HC574TTR level) and while OE is in high level the outputs will be in a high impedance state. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 M74HC574 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE OE H L L L X: Don’t Care Z: High Impedance LOGIC DIAGRAM INPUTS CK X PIN DESCRIPTION
PIN No 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 NAME AND FUNCTION 3 State Output Enable Input (Active LOW) Data Inputs Q7 to Q0 3 State Outputs CK GND VCC Clock Input (LOW to HIGH, edge triggered) Ground (0V) Positive Supply Voltag...
STMicroelectronics
