DESCRIPTION
A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low on the appropriate input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection October 1992 1/11 M54/M74HC74 TRUTH TABLE INPUTS CLR L H L H H H X: Don’t Care OUTPUTS D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn PR H L L H H H FUNCTION CLEAR PRESET NO CHANGE PIN DESCRIPTION
PIN No 1, 13 2, 12 3, 11 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK NAME AND FUNCTION Asyncronous Reset Direct Input Data Inputs Clock Input (LOW-to-HIGH, EdgeTriggered) Asyncronous Set - Direct Input True Flip-Flop Outpus Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOL 4, 10 5, 9 6, 8 7 14 1PR, 2PR 1Q, 2Q 1Q, 2Q GND V CC LOGIC DIAGRAM 2/11 M54/M74HC74...
STMicroelectronics
