STMicroelectronics MK50H25
The MK50H25 will perform frame formating including: frame delimiting with flags, transparency (so-called ”bit-stuffing”), error recovery by retransmission, sequence number control, S (supervisory) and U (unnumbered) frame control, plus FCS (CRC) generation and detection. The MK50H25 also supports X.75 and X.32 (with its XID frame support), as well as single channel ISDN LAPD (with its support of UI frames and extended addressing capabilities). This flexible transparent mode may be easily entered and exited without affecting the X.25 link status or the link state variables kept by the MK50H25.
| Part No. |
MK50H25 |
| Datasheet |
MK50H25
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| Manufacturer |
 STMicroelectronics |
| Description |
HIGH SPEED LINK LEVEL CONTROLLER |
| Buy |
Stock & Price
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FEATURES
System clock rate up to 33 MHz (MK50H25 33), 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst length. DMA transfer rate of up to 13.3 Mbytes/sec using optional 5 SYSCLK DMA cycle (150 nS) at 33 MHz SYSCLK. Complete Level 2 implementation compatible with X.25 LAPB, ISDN LAPD, X.32, and X.75 Protocols. Handles all error recovery, sequencing, and S and U frame control. Pin-for-pin and architecturally compatible with MK5025 (X.25/LAPD), MK5027 (CCS#7) and MK5029(SDLC). Buffer Management includes: - Initialization Block - Separate Receive and Transmit Rings - Variable Descriptor Ring and Window Sizes. Separate 64-byte Transmit and Receive FIFO. Programmable Transmit FIFO hold-off watermark. Handles all HDLC frame formatting: - Zero bit insertion and deletion - FCS (CRC) generation and detection - Frame delimiting with flags Programmable Single or Extended Address and Control fields.
