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MK50H28 Datasheet PDF

STMicroelectronics MK50H28

The MK50H28 will perform frame formating including: frame delimiting with flags, transparency (so-called ”bitstuffing”), plus FCS (CRC) generation and detection. It also supports Local Management Interface (LMI) protocol with the ”Optional Bidirectional Procedures” (Annex D, T1.617 - 1991 and T1.617a1994). This feature allows users to receive and transmit multiple data frames at a time.
Part No. MK50H28
Datasheet MK50H28 Download
Manufacturer
STMicroelectronics
Description MULTI LOGICAL LINK FRAME RELAY CONTROLLER
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MK50H28 datasheet page 1 preview

FEATURES

Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits(PVCs). Optional Transparent Mode (no LMI Protocol Processing - all frame data received). Local Management Link Protocol with optional Bi-directional message processing. Detects and indicates service-affecting errors in the timing or content of events. Programmable Timers/Counters: nT1/T391, nT2/T392, nN1/N391, nN2/N392, nN3/N393 and dN1 for the LMI/LIV channel. Provides Error Counters for the LMI channel and Congestion Statistics for all the active channels. LMI/LIV Frames can be transmitted/received on DLCI 0 or 1023. Supports reception of up to 4 octets of address field with a maximum of 8192 active channels or DLCIs (Data Link Connection Identifiers) Priority DLCI scheme for channels requiring higher rate of service. Buffer Management includes: - Initialization Block - Address Look Up Table - Context Table - Separate Receive and Transmit Rings of variable size for each active channel On chip DMA control with programmable burst length.
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