PSD835G2 Key Features
- Flash in-system programmable (ISP) peripheral for 8-bit MCUs
- Dual bank flash memories
- 4 Mbits of primary Flash memory (8 uniform sectors, 64 Kbytes)
- 256 Kbits of secondary Flash memory with 4 sectors
- Concurrent operation: READ from one memory while erasing and writing the other
- 64 Kbit of SRAM
- 52 reconfigurable I/O ports
- Enhanced JTAG serial port
- PLD with macrocells
- Over 3000 gates of PLD: CPLD and DPLD