Full PDF Text Transcription for PSD835G2 (Reference)
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PSD835G2. For precise diagrams, and layout, please refer to the original PDF.
PSD835G2 Flash PSD, 5 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM Features ■ Flash in-system programmable (ISP) peripheral for 8-bit M...
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M Features ■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs ■ Dual bank flash memories – 4 Mbits of primary Flash memory (8 uniform sectors, 64 Kbytes) – 256 Kbits of secondary Flash memory with 4 sectors – Concurrent operation: READ from one memory while erasing and writing the other ■ 64 Kbit of SRAM ■ 52 reconfigurable I/O ports ■ Enhanced JTAG serial port ■ PLD with macrocells – Over 3000 gates of PLD: CPLD and DPLD – CPLD with 16 output macrocells (OMCs) and 24 Rev 5 macrocells (IMCs) – DPLD - user defined internal chip select decoding ■ 52 individually configurable I/O port pins They can be used for the
PSD835G2 Datasheet
