SPC560P40L1 Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 Device parison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 Block diagram . . . . . . . . . . . . . . . .
SPC560P40L1 Key Features
- Up to 64 MHz, single issue, 32-bit CPU core plex (e200z0h)
- pliant with Power Architecture® embedded category
- Variable Length Encoding (VLE)
- Memory organization
- Up to 256 KB on-chip code flash memory with ECC and erase/program controller
- Additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation
- Up to 20 KB on-chip SRAM with ECC
- Fail-safe protection
- Programmable watchdog timer
- Non-maskable interrupt
SPC560P40L1 Applications
- Up to 64 MHz, single issue, 32-bit CPU core plex (e200z0h)
- pliant with Power Architecture® embedded category