Datasheet4U Logo Datasheet4U.com

SPC560P40L1 - 32-bit MCU

Download the SPC560P40L1 datasheet PDF. This datasheet also covers the SPC560P34L1 variant, as both devices belong to the same 32-bit mcu family and are provided as variant models within a single manufacturer datasheet.

General Description

.

.

.

.

.

.

.

.

9 1.

Key Features

  • Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h).
  • Compliant with Power Architecture® embedded category.
  • Variable Length Encoding (VLE).
  • Memory organization.
  • Up to 256 KB on-chip code flash memory with ECC and erase/program controller.
  • Additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation.
  • Up to 20 KB on-chip SRAM with ECC.
  • Fail-safe protection.
  • Programmable watchdog timer.
  • Non-.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SPC560P34L1-STMicroelectronics.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SPC560P34L1, SPC560P34L3 SPC560P40L1, SPC560P40L3 32-bit Power Architecture® based MCU with 320 KB Flash memory and 20 KB RAM for automotive chassis and safety applications Datasheet − production data Features ■ Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h) – Compliant with Power Architecture® embedded category – Variable Length Encoding (VLE) ■ Memory organization – Up to 256 KB on-chip code flash memory with ECC and erase/program controller – Additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation – Up to 20 KB on-chip SRAM with ECC ■ Fail-safe protection – Programmable watchdog timer – Non-maskable interrupt – Fault collection unit ■ Nexus Class 1 interface ■ Interrupts and events – 16-channel eDMA controller – 16 priority level controller – Up