SPC560P60L3
Features
- AEC-Q10x qualified
- 64 MHz, single issue, 32-bit CPU core plex (e200z0h)
- pliant with Power Architecture® embedded category
- Variable Length Encoding (VLE)
- Memory organization
- Up to 1024 KB on-chip code Flash memory with additional 64 KB for EEPROM emulation (data flash), with ECC, with erase/program controller
- Up to 80 KB on-chip SRAM with ECC
- Fail safe protection
- ECC protection on system SRAM and Flash
- Safety port
- SWT with servicing sequence pseudorandom generator
- Power management
- Non-maskable interrupt for both cores
- Fault collection and control unit (FCCU)
- Safe mode of system-on-chip (So C)
- Register protection scheme
- Nexus® L2+ interface
- Single 3.3 V or 5 V supply for I/Os and ADC
- 2 on-platform peripherals set with 2 INTC
- 16-channel e DMA controller with multiple transfer request sources
- General purpose I/Os (80 GPIO + 26 GPI on LQFP144; 49 GPIO + 16 GPI on LQFP100)
- 2 general purpose e Timer units
- 6 timers, each with up/down count...
