SPC560P60L5
Key Features
- AEC-Q10x qualified
- 64 MHz, single issue, 32-bit CPU core plex (e200z0h) – compliant with Power Architecture® embedded category – Variable Length Encoding (VLE)
- Nexus® L2+ interface
- Single 3.3 V or 5 V supply for I/Os and ADC
- 2 on-platform peripherals set with 2 INTC
- 16-channel eDMA controller with multiple transfer request sources
- General purpose I/Os (80 GPIO + 26 GPI on LQFP144; 49 GPIO + 16 GPI on LQFP100)
- 2 CRC units with three contexts and 3 hardwired polynomials(CRC8,CRC32 and CRC-16-CCITT)
- On-chip CAN/UART Bootstrap loader with boot assist module (BAM)
