STMicroelectronics SPC58NE84C3
the SPC58NExx family microcontroller unit (MCU). This document is preliminary and subject to any change without notification.FEATURES
● Two 32-bit Power Architecture® VLE compliant CPU core (e200z4d), dual issue, one of them being paired in lockstep – Single-precision floating point operations – 8 kB I-Cache and 4 kB D-Cache – 16 kB local instruction SRAM and 64 kB local data SRAM● One 32-bit Power Architecture® VLE compliant CPU core (e200z4d), dual issue, paired in lockstep – Single-precision floating point operations – Lightweight Signal Processing Auxiliary Processing Unit (LSP APU) instruction support for digital signal processing (DSP) – 8 kB I-Cache – 16 kB local instruction SRAM and 32 kB local data SRAM
● 6320 kB on-chip flash memory – Supporting EEPROM emulation (256 kB) – 2 Flash Controller supporting true ReadWhile-Read Flash access (RWR)
● 608 kB on-chip general-purpose SRAM (+160 kB data RAM included in the CPUs)
● Multi-channel direct memory access controller (eDMA) with 96 channels, paired in lock-step
● Dual phase-locked loops, including one frequency-modulated
● Hardware Security Module (H...