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SPEAR-09-B042 - large IP portfolio SoC

General Description

SPEAr BASIC is a powerful digital engine belonging to SPEAr family, the innovative customizable system-on-chip.

The device integrates an ARM 926 core with an extensive set of proven IPs and a large configurable logic block that allows very fast customization of unique and/or proprietary solutions.

Key Features

  • ARM926EJ-S core @333 MHz.
  • 16 Kbyte instructions/data cache Reconfigurable logic array:.
  • 300 Kgate (100% utilization rate).
  • 102 I/O lines.
  • No clock domain limitation.
  • 64 Kbyte + 8 Kbyte configurable memory pool Multilayer AMBA 2.0 compliant bus with fMAX 166 MHz 32-Kbyte boot ROM 8 Kbyte common static RAM.
  • Shared with reconfigurable array Dynamic power saving features High performance DMA.
  • 8 channels Ethernet 10/100 MAC w.

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Full PDF Text Transcription for SPEAR-09-B042 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for SPEAR-09-B042. For precise diagrams, and layout, please refer to the original PDF.

SPEAR-09-B042 SPEAr® BASIC ARM 926EJ-S core, customizable logic, large IP portfolio SoC Preliminary Data Features ■ ■ ARM926EJ-S core @333 MHz – 16 Kbyte instructions/dat...

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Data Features ■ ■ ARM926EJ-S core @333 MHz – 16 Kbyte instructions/data cache Reconfigurable logic array: – 300 Kgate (100% utilization rate) – 102 I/O lines – No clock domain limitation – 64 Kbyte + 8 Kbyte configurable memory pool Multilayer AMBA 2.0 compliant bus with fMAX 166 MHz 32-Kbyte boot ROM 8 Kbyte common static RAM – Shared with reconfigurable array Dynamic power saving features High performance DMA – 8 channels Ethernet 10/100 MAC with MII interface. (IEEE-802.3) USB 2.0 device with integrated PHY ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LFBGA289 6 legacy GPIO bidirectional signals with interrupt capability ADC 10-bit, 1 Msp

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