DESCRIPTION
The memory is arranged as a matrix of 24x8 cells, accessed in a serial bit- Figure 1. Logic Diagram VCC RST ST1305B I/O Table 1. Signal Names CLK RST I/O VCC GND Clock Reset Serial Data Input/Output Supply Voltage Ground CLK GND DS05B01 October 1999 Complete data available under NDA. 1/2 ST1305B wise fashion for reading and programming, and in a byte-wise fashion for internal erasing. The device recognises three commands issued via the RST and CLK pins (as described in the full data sheet): – RESET: to reset the internal address register to 00d – READ: to increment the internal address register, and read the data bit at that address – PROG: to program the bit at the current address. Figure 2. Memory Map In USER Configuration 000d 016d Card Identification 48 bits EEPROM Cells Matrix Circuit Identification 16 bits READ ONLY The device offers two distinct configurations: – ISSUER: for the card manufacturer, allowing special data to be written to the chip, during initialisation – USER: for the end user of the card, restricting access to the chip.
STMicroelectronics
