DESCRIPTION
The memory is arranged as a matrix of 24x8 cells, accessed in a serial bit-wise fashion for reading and programming, and in a byte-wise fashion Table 1. Signal Names for internal erasing. CLK Clock The device recognises three commands issued via the RST and CLK pins (as described in the full data sheet): – RESET: to reset the internal address register to 00d – READ: to increment the internal address register, and read the data bit at that address – PROG: to program the bit at the current address. RST I/O VCC GND Reset Serial Data Input/Output Supply Voltage Ground AI01032 BD.05/9803V1 1/2 ST1305 The device offers two distinct configurations: – ISSUER: for the card manufacturer, allowing special data to be written to the chip, during initialisation – USER: for the end user of the card, restricting access to the chip. Before delivery, from ST to the card issuer, the device is placed in the ISSUER configuration. This operation is performed by blowing the “test fuse”. Figure 3.
STMicroelectronics
