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STM32H503CB - 32-bit MCU+FPU

Download the STM32H503CB datasheet PDF. This datasheet also covers the STM32H503EB variant, as both devices belong to the same 32-bit mcu+fpu family and are provided as variant models within a single manufacturer datasheet.

General Description

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16 3.1 Arm Cortex-M33 core with FPU

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Key Features

  • Includes ST state-of-the-art patented technology Core.
  • Arm® Cortex®-M33 CPU with FPU, frequency up to 250 MHz, MPU, 375 DMIPS (Dhrystone 2.1), and DSP instructions ART Accelerator.
  • 8-Kbyte instruction cache allowing 0-wait-state execution from flash memory (frequency up to 250 MHz) Benchmarks.
  • 1.5 DMIPS/MHz (Drystone 2.1).
  • 1023 CoreMark® (4.092 CoreMark®/MHz) Memories.
  • 128 Kbytes of embedded flash memory with ECC, two banks of read-while-write.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (STM32H503EB-STMicroelectronics.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by STMicroelectronics

Part Number Description
STM32H503EB 32-bit MCU+FPU
STM32H503KB 32-bit MCU+FPU
STM32H503RB 32-bit MCU+FPU
STM32H523CC 32-bit MCU
STM32H523CE 32-bit MCU

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
STM32H503xx Arm® Cortex®-M33 32-bit MCU+FPU, 375 DMIPS, 250 MHz, 128 Kbytes flash memory, 32 Kbytes RAM, I3C Datasheet - production data Features Includes ST state-of-the-art patented technology Core • Arm® Cortex®-M33 CPU with FPU, frequency up to 250 MHz, MPU, 375 DMIPS (Dhrystone 2.1), and DSP instructions ART Accelerator • 8-Kbyte instruction cache allowing 0-wait-state execution from flash memory (frequency up to 250 MHz) Benchmarks • 1.5 DMIPS/MHz (Drystone 2.1) • 1023 CoreMark® (4.092 CoreMark®/MHz) Memories • 128 Kbytes of embedded flash memory with ECC, two banks of read-while-write • 2-Kbyte OTP (one-time programmable) • 32-Kbyte SRAM with ECC • 2 Kbytes of backup SRAM (available in the lowest power modes) Clock, reset, and supply management • 1.71 V to 3.