STM8AF6366 Description
14 5.1 STM8A central processing unit (CPU) . 14 5.1.1 Architecture and registers.
STM8AF6366 Key Features
- AEC-Q10x qualified
- Max fCPU: 16 MHz
- Advanced STM8A core with Harvard architecture and 3-stage pipeline
- Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark
- Memories
- Flash Program memory: 16 to 32 Kbyte Flash; data retention 20 years at 55 °C after 1 kcycle
- Data memory: 0.5 to 1 Kbyte true data EEPROM; endurance 300 kcycle
- RAM: 2 Kbyte
- Clock management
- Low-power crystal resonator oscillator with external clock input