STM8S007C8 Description
11 4.1 Central processing unit STM8 . .11 4.2 Single wire interface module (SWIM) and debug module (DM) . 12 4.3 Interrupt controller.
STM8S007C8 Key Features
- Max fCPU: up to 24 MHz, 0 wait states @
- Advanced STM8 core with Harvard architecture and 3-stage pipeline
- Extended instruction set
- Max 20 MIPS @ 24 MHz
- Memories
- Program: 64 Kbytes Flash; data retention 20 years at 55 °C after 100 cycles
- Data: 128 bytes true data EEPROM; endurance 100 kcycles
- RAM: 6 Kbytes
- Clock, reset and supply management
- 2.95 to 5.5 V operating voltage