STM8S105S6 Description
13 4.1 Central processing unit STM8 . 13 4.2 Single wire interface module (SWIM) and debug module (DM) . 14 4.3 Interrupt controller.
STM8S105S6 Key Features
- 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
- Extended instruction set
- Program memory: up to 32 Kbyte Flash; data retention 20 years at 55 °C after 10 kcycle
- Data memory: up to 1 Kbyte true data EEPROM; endurance 300 kcycle
- RAM: up to 2 Kbyte
- 2.95 to 5.5 V operating voltage
- Flexible clock control, 4 master clock sources
- Low power crystal resonator oscillator
- External clock input
- Internal, user-trimmable 16 MHz RC