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TDA7333N
RDS/RBDS processor
Features
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3rd order high resolution sigma delta converter for MPX sampling Digital decimation and filtering stages Demodulation of european radio data system (RDS) Demodulation of USA radio broadcast data system (RBDS) Automatic group and block synchronization with flywheel mechanism Error detection and correction RAM buffer with a storage capacity of 24 RDS blocks and related status information Programmable interrupt source (RDS block A, B, or D, TA, TA EON) I2C/SPI bus interface Input frequency range 4-21 MHz Power down mode 3.3 V power supply, 0.35 µm CMOS technology Device summary
Operating temp.