SDD50N03L Overview
S amHop Microelectronics C orp. May,2004 ver1.1 N-C hannel Logic Level E nhancement Mode Field E ffect Transistor P R ODUC T S UMMAR Y 47A R DS (ON) S uper high dense cell design for low R DS (ON ). 8 @ V G S = 10V 12 @ V G S = 4.5V R ugged and reliable. TO-252 and TO-251 P ackage. G D S G S DU S E R IE S TO-252AA(D-P AK) S DD S E R IE S TO-251(l-P AK) S ABS OLUTE MAXIMUM R ATINGS (T C =25 C unless otherwise noted) P arameter Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous -P ulsed Thermal R esistance, Junction-to-C ase Thermal R esistance, Junction-to-Ambient