STD410S Overview
S T U/D410S S amHop Microelectronics C orp. 26 2007 N-C hannel Logic Level E nhancement Mode Field E ffect Transistor P R ODUC T S UMMAR Y V DS S 40V F E AT UR E S S uper high dense cell design for low R DS (ON ). ID 30A R DS (ON) ( m W ) Max 20 @ V G S = 10V 30 @ V G S = 4.5V R ugged and reliable.