STU1855PL Datasheet PDF

S T U/D1855P L S amHop Microelectronics C orp. Arp,20 2005 ver1.1 P -C hannel E nhancement Mode Field E ffect Transistor P R ODUC T S UMMAR Y V DS S -55V F E AT UR E S ( m W ) Max ID -15A R DS (ON) S uper high dense cell design for low R DS (ON ). 68 @ V G S = -10V 85 @ V G S = -4.5V R ugged and reliable. TO-252 and TO-251 P ackage. D D G S G D S G S TU S E R IE S TO-252AA(D-P AK) S TD S E R IE S TO-251(l-P AK) S AB S OL UTE MAXIMUM R ATINGS P arameter Drain-S ource Voltage R ating Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous @ Ta -P ulsed b a (T A =25 C unles s otherwis e noted) S ymbol Vspike d V DS V GS Limit 60 -55 20 -15 -12 -30 -10 42 28 -55 to 150 W C Unit V V V A A A A 25 C 70 C ID IDM IS PD T J , T S TG Drain-S ource Diode Forward C urrent a Maximum P ower Dissipation a Operating Junction and S torage Temperature R ange Ta= 25 C Ta=70 C THE R MAL C HAR AC TE R IS TIC S Thermal R esistance, Junction-to-C ase Thermal R esistance, Junction-to-Ambient 1 R...