STU3055L Datasheet PDF

S T U/D3055L S amHop Microelectronics C orp. MAR ,09 2005 ver1.1 N-C hannel Logic Level E nhancement Mode Field E ffect Transistor P R ODUC T S UMMAR Y V DS S 25V F E AT UR E S ( mW) ID 12A R DS (ON) Max S uper high dense cell design for low R DS (ON ). 70 @ V G S = 10V 95 @ V G S = 4.5V R ugged and reliable. TO-252 and TO-251 P ackage. D D G S G D S G S TU S E R IE S TO-252AA(D-P AK) S TD S E R IE S TO-251(l-P AK) S ABS OLUTE MAXIMUM R ATINGS (T C =25 C unless otherwise noted) P arameter Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous a -P ulsed @ TJ=25 C S ymbol V DS V GS ID IDM IS PD T J , T S TG Limit 25 16 12 40 5 50 -55 to 175 Unit V V A A A W C Drain-S ource Diode Forward C urrent Maximum P ower Dissipation @ Tc=25 C Operating and S torage Temperature R ange THE R MAL C HAR AC TE R IS TIC S Thermal R esistance, Junction-to-C ase Thermal R esistance, Junction-to-Ambient R JC R JA 3 50 C /W C /W 1 S T U/D3055L E LE CTR ICAL CHAR ACTE R IS TICS (T A =25 C unle...