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K4H1G0638B - DDR SDRAM stacked 1Gb B-die (x4/x8)

General Description

DDR SDRAM st.128Mb x 8 st.256Mb x 4 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS0 CS1 BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS0 CS1 BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6

Key Features

  • Double-data-rate architecture; two data transfers per clock cycle.
  • Bidirectional data strobe DQS.
  • Four banks operation.
  • Differential clock inputs(CK and CK).
  • DLL aligns DQ and DQS transition with CK transition.
  • MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave).
  • All inputs except data & DM are sampled at the positive going edge of the system clock(CK).

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Datasheet Details

Part number K4H1G0638B
Manufacturer Samsung Electronics
File Size 237.59 KB
Description DDR SDRAM stacked 1Gb B-die (x4/x8)
Datasheet download datasheet K4H1G0638B Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com DDR SDRAM stacked 1Gb B-die (x4/x8) DDR SDRAM Stacked 1Gb B-die DDR SDRAM Specification (x4/x8) Revision 1.1 Rev. 1.1 August. 2003 www.DataSheet4U.com DDR SDRAM stacked 1Gb B-die (x4/x8) st. 1Gb B-die Revision History Revision 0.0 (May, 2003) - First version for internal review. Revision 1.0 (June, 2003) - Deleted "B3" speed. Revision 1.1 (August, 2003) - Corrected typo. DDR SDRAM Rev. 1.1 August. 2003 www.DataSheet4U.com DDR SDRAM stacked 1Gb B-die (x4/x8) Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe DQS • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -.