K4H1G0738B Overview
Row & Column address configuration Rev. DDR SDRAM stacked 1Gb B-die (x4/x8) Package Physical.
K4H1G0738B Key Features
- Double-data-rate architecture; two data transfers per clock cycle
- Bidirectional data strobe DQS
- Four banks operation
- Differential clock inputs(CK and CK)
- DLL aligns DQ and DQS transition with CK transition
- MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential &
- All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
- Data I/O transactions on both edges of data strobe
- Edge aligned data output, center aligned data input
- DM for write masking only (x4, x8)