Description
DDR SDRAM
st.128Mb x 8 st.256Mb x 4
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS0 CS1 BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS0 CS1 BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6
Features
- Double-data-rate architecture; two data transfers per clock cycle.
- Bidirectional data strobe DQS.
- Four banks operation.
- Differential clock inputs(CK and CK).
- DLL aligns DQ and DQS transition with CK transition.
- MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave).
- All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
K4H1G0738B Datasheet
