K4Q153212M Datasheet | Samsung Semiconductor

DESCRIPTION CMOS DRAM This is a 524,288 x 32 bit Extended Data Out CMOS DRAM. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle 1K, access time (-50 or -60), power consumption(Normal or Low power) and SOJ package type are optional features of this family. All of this family have CAS-before RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 512Kx32 EDO Mode Quad CAS DRAM is fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability. FEATURES - Part Identification - K4Q153211M-JC (5.0V, 1K Ref.) - K4Q153211M-JL (5.0V, 1K Ref. LP) - K4Q153212M-JC (3.3V, 1K Ref.) - K4Q153212M-JL (3.3V, 1K Ref. LP) - Extended Data Out Mode operation (Fast Page Mode with Extended Data Out) - Four separate CAS pins provide for separate I/O operation - CAS-before-RAS refresh capability - RAS-only and Hidden refresh capability - Self-refresh capability (L-ver only) - TTL(5V)/LVTTL(3.3V) patible inputs and outputs - Early Write or output enable controlled write - JEDEC Standard pinout - Plastic SOJ 400mil x 1125mil package - Single +5.0V±0.5V power supply(5V product) - Single +3.3V±0.3V power supply(3.3V product) - Active Power Dissipation Speed -50 -60 3.3V 540 Unit : m W 5.0V 880 825 FUNCTIONAL BLOCK DIAGRAM - Refresh Cycles Part NO. 153211M-J 153212M-J VCC 5.0V 3.3V Refresh cycle 1K 1K Refresh period Normal 16ms 16ms L-ver 128ms 128ms Refresh Timer Refresh Control Row Decoder Sense Amps & I/O RAS CAS0-3 W Control Clocks VBB Generator Vcc Vss CAS0 D/I Buffer CAS0 D/O Buffer CAS1 D/I Buffer CAS1 D/O Buffer OE CAS2 D/I Buffer CAS2 D/O Buffer CAS3 D/I Buffer CAS3 D/O Buffer DQ16 to DQ23 DQ0 to DQ7 DQ8 to DQ15 - Performance Range Speed -50 -60 Refresh Counter t RAC 50ns 60ns t CAC 15ns 17ns t RC 84ns 104ns t HPC 20ns...